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EDI8F82045C
2Megx8 SRAM Module
Features
2 Meg x 8 bit CMOS Static Random Access Memory * Access Times 70 thru 100ns * Data Retention Function (EDI8F82045LP ) * TTL Compatible Inputs and Outputs * Fully Static, No Clocks High Density Packaging * 36 Pin DIP, No. 177 Single +5V (10%) Supply Operation
2 Megabits x 8 Static RAM CMOS, Module
The EDI8F82045C is a 16 megabit CMOS Static RAM based on four 512Kx8 Static RAMs mounted on a multi-layered epoxy laminate (FR4) substrate. A low power version with data retention (EDI8F82045LP) is also available. All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous, the EDI8F82045C requires no clocks or refreshing for operation.
Pin Configurations and Block Diagram
Pin Names
AO-A20 Pin Names E W G DQO-DQ7 VCC VSS NC Address Inputs Chip Enable Write Enable Output Enable Common Data Input/Output Power (+5V10%) Ground No Connection
NC A19 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AO DQO DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VCC A20 NC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AO-A18 W G
DQO-DQ7
A19-A20 E
DEC
Electronic Designs Incorporated * One Research Drive * Westborough, MA 01581USA * 508-366-5151 * FAX 508-836-4850 * Electronic Designs Europe Ltd. * Shelley House, The Avenue * Lightwater, Surrey GU18 5RF United Kingdom * 01276 472637 * FAX: 01276 473748 1 EDI8F82045C Rev. 5.0 6/96 ECO#7549
Absolute Maximum Ratings*
Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. -0.5V to 7.0V 0C to +70C -40C to +85C -55C to +125C 1 Watt 20 mA
Recommended DC Operating Conditions
Parameter Sym Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --Max Units 5.5 V 0 V 6.0 V 0.8 V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
VSS to 3.0V 5ns 1.5V 1TTL, CL =100pF
DC Electrical Characteristics
Parameter Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current (CMOS) Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
*Typical: TA = 25C, VCC = 5.0V
Sym ICC1 ICC2 ICC3
ILI ILO VOH VOL
Conditions W, E = VIL, II/O = 0mA, Min Cycle E VIH, VIN VIL VIN VIH E VCC-0.2V VIN VCC-0.2V or VIN 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH =-1.0mA IOL = 2.1mA
Min --C LP ---10 -10 2.4 --
Typ*
Max 150 55
Units mA mA mA A A A V V
2 450 -----
3 600 10 10 -0.4
Truth Table
G X H L X E H L L L W X H H L Mode Standby Output Deselect Read Write Output High Z High Z DOUT DIN Power ICC2, ICC3 ICC1 ICC1 ICC1
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter Sym Address Lines CI Data Lines CD/Q Chip Enable Line CC Write and Output Enable Lines CW Max 30 43 10 32 Unit pF pF pF pF
These parameters are sampled, not 100% tested.
EDI8F82045C
2Megx8 SRAM Module
2 EDI8F82045C Rev. 5.0 6/96 ECO#7549
EDI8F82045C
2Megx8 SRAM Module
AC Characteristics Read Cycle
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1)
NOTE 1: Parameter guaranteed, but not tested.
Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ
70ns Min Max 70 70 70 5 30 5 40 5 30
85ns Min Max 85 85 85 5 35 5 45 5 35
100ns Min Max 100 100 100 5 40 5 50 5 40
Units ns ns ns ns ns ns ns ns ns
Read Cycle 1 - W High, G, E Low
TAVAV A ADDRESS 1 TAVQV Q ADDRESS 2 TAVQX DATA 1 DATA 2
Read Cycle 2 - W High
TAVAV A TAVQV E TELQV TELQX G TGLQV TGLQX Q TGHQZ TEHQZ
3 EDI8F82045C Rev. 5.0 6/96 ECO#7549
AC Characteristics Write Cycle
Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
Symbol JEDEC Alt. TAVAV TWC TELWH TCW TELEH TCW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TWLEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ
70ns Min Max 70 65 65 0 0 65 65 65 65 5 5 0 0 0 30 30 30 5
85ns Min Max 85 70 70 0 0 70 70 70 70 5 5 0 0 0 35 35 35 5
100ns Min Max 100 80 80 0 0 80 80 80 80 5 5 0 0 0 40 40 40 5
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle 1 - W Controlled
TAVAV A E TELWH TAVWH TWLWH W TAVWL D TWLQZ Q HIGH Z TDVWH DATA VALID TWHQX TWHDX TWHAX
EDI8F82045C
2Megx8 SRAM Module
4 EDI8F82045C Rev. 5.0 6/96 ECO#7549
EDI8F82045C
2Megx8 SRAM Module
Write Cycle 2 - E Controlled
TAVAV A TAVEL E TAVEH TWLEH W TDVEH D Q HIGH Z DATA VALID TEHDX TEHAX TELEH
Data Retention Characteristics
Characteristic Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time
Note 1: Parameter guaranteed, but not tested. * Read Cycle Time
LP Version Only
Sym VDD ICCDR TCDR(1) TR(1) Test Conditions VDD Min 2 -0 TAVAV* Typ -Max 70 C 85C --200 260 320 420 ----Unit V A A ns ns
E VDD -0.2V VIN VDD -0.2V or VIN 0.2V
2V 3V
---
Data Retention - E Controlled
Data Retention Mode VCC TCDR 4.5V VDD 4.5V
TR
E
EVDD -0.2V
5 EDI8F82045C Rev. 5.0 6/96 ECO#7549
Ordering Information
Standard Power EDI8F82045C70B6C EDI8F82045C85B6C EDI8F82045C100B6C Low Power with Data Retention EDI8F82045LP70B6C EDI8F82045LP85B6C EDI8F82045LP100B6C Speed (ns) 70 85 100 Package No. 177 177 177
To order an Industrial grade product substitute the letter C in the Suffix with the letter I, eg. EDI8F82045C70B6C becomes EDI8F82045C70B6I.
Package Description Package No. 177 36 Pin Dual-in-line Package
2.010 MAX
0.670 MAX
0.010 0.005
0.220 MAX 0.175 0.125
0.150 Ref
0.100 Typ 17 x 0.100 1.700 Ref.
0.620 0.590
Electronic Designs Incorporated * One Research Drive * Westborough, MA 01581USA * 508-366-5151 * FAX 508-836-4850 * Electronic Designs Europe Ltd. * Shelley House, The Avenue * Lightwater, Surrey GU18 5RF United Kingdom * 01276 472637 * FAX: 01276 473748 Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301
EDI8F82045C
2Megx8 SRAM Module
6 EDI8F82045C Rev. 5.0 6/96 ECO#7549

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